Edition README
PRISM-1
README.md
1 # Komorebi PRISM-1 final updated architecture
2
3 **Projector-Resolved Integrated Signal Machine**
4
5 PRISM-1 is a packet-programmable mixed-representation processor for Projector-Resolved Seed Calculus and PR-LASM workloads. A program may remain in block, low-rank, Kronecker, sparse-factor, transform, packet-graph, or explicit-array form. The chip preserves the requested output contract rather than an unnecessary dense intermediate.
6
7 ## Release contents
8
9 - final updated architecture paper
10 - 43 vector-PDF and 43 PNG figures
11 - executable architecture, planning, and performance model
12 - 18 behavioral self-tests
13 - 18 independent tests
14 - four Packet IR examples
15 - eleven SystemVerilog boundary modules
16 - data sheet, command specification, compiler specification, and microarchitecture notes
17 - machine-readable results, manifest, and checksums
18
19 ## Reference configuration
20
21 - 4 compute chiplets
22 - 16 Packet Streaming Multiprocessors per chiplet
23 - 64 Packet Streaming Multiprocessors total
24 - 4 execution groups per multiprocessor
25 - 256 execution groups total
26 - one 16 by 16 matrix array plus vector lanes per execution group
27 - 2 MiB packet scratchpad per multiprocessor
28 - 32 transform engines
29 - 16 small-solver engines
30 - 4 exact-arithmetic clusters
31 - 192 MiB total local and shared SRAM
32 - 4 HBM4 stacks with 144 GiB reference capacity
33 - more than 11.2 TB/s aggregate reference HBM bandwidth
34 - UCIe 3.0 class package links
35 - PCIe 7.0 x16 class host attachment
36 - 500 W package target
37
38 These are architecture targets, not measured silicon results.
39
40 ## Run the model and tests
41
42 Linux or WSL:
43
44 ```bash
45 ./run_all.sh
46 ```
47
48 PowerShell:
49
50 ```powershell
51 & .\Run_All.ps1
52 ```
53
54 Direct commands:
55
56 ```bash
57 python prism_chip_model.py --root .
58 PYTHONPATH=. python -m pytest -q
59 ```
60
61 ## Build the paper
62
63 ```bash
64 latexmk -pdf -interaction=nonstopmode -halt-on-error Komorebi_PRISM_1_Final_Updated.tex
65 ```
66
67 ## Design boundary
68
69 The package contains a behavioral architecture, a mixed-representation planner, a CUDA-compatible Packet IR, an executable cost model, and RTL boundary modules. It does not contain completed production RTL, synthesis, static timing, place and route, or measured FPGA or silicon performance.