README.md
PRISM-1
README.md
1 # PRISM-1 RTL boundary modules
2
3 These files define control and interface boundaries for the final updated architecture. They are not production RTL. No HDL simulation, synthesis, timing, formal verification, or place-and-route result is claimed.
4
5 ## Modules
6
7 - `prism_descriptor_pkg.sv` defines opcodes and packed records
8 - `prism_command_fifo.sv` buffers commands
9 - `prism_token_scoreboard.sv` tracks dependency tokens
10 - `prism_packet_directory.sv` tracks packet representation and state
11 - `prism_representation_router.sv` chooses an execution form
12 - `prism_psm_scheduler.sv` issues packet warps to execution groups
13 - `prism_execution_group.sv` defines one matrix and vector execution boundary
14 - `prism_residual_accumulator.sv` accumulates a wide residual
15 - `prism_commit_controller.sv` chooses commit, replay, or abort
16 - `prism_tile_shell.sv` remains a compatibility wrapper for staged bring-up
17 - `prism_top.sv` defines the queue-facing top-level shell
18
19 The next hardware milestone is a bit-accurate FPGA Packet Streaming Multiprocessor using the same descriptor and Packet IR contracts.