PRISM-1

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1 \begin{longtable}{L{0.42\linewidth}L{0.46\linewidth}}
2 \toprule
3 Item & PRISM-1 reference target \\
4 \midrule
5 \endfirsthead
6 \toprule
7 Item & PRISM-1 reference target \\
8 \midrule
9 \endhead
10 Compute chiplets & 4 \\
11 Packet Streaming Multiprocessors & 64 total, 16 per compute chiplet \\
12 Packet execution groups & 256 total, 4 per multiprocessor \\
13 Execution group & $16\times16$ matrix array plus programmable vector lanes \\
14 Clock & 1.5 GHz model target \\
15 Packet scratchpad & 2 MiB per multiprocessor across four banked regions \\
16 Shared SRAM & 16 MiB per compute chiplet \\
17 Total local and shared SRAM & 192 MiB \\
18 FP16 and BF16 model peak & 196.6 TFLOP/s \\
19 FP32 model peak & 98.3 TFLOP/s \\
20 FP64 model peak & 24.6 TFLOP/s \\
21 Transform engines & 32 \\
22 Small-solver engines & 16 \\
23 Exact arithmetic clusters & 4 \\
24 HBM4 & 4 stacks \\
25 HBM capacity & 144 GiB \\
26 HBM bandwidth & greater than 11.2 TB/s aggregate \\
27 Package links & UCIe 3.0 class at up to 64 GT/s \\
28 Host link & PCIe 7.0 x16 class, optional CXL \\
29 Power target & 500 W \\
30 Representation forms & explicit array, block, block sparse, low rank, BDLR, Kronecker, sparse factor chain, transform plan, packet graph \\
31 Output contracts & apply, compressed operator, factor graph, transform plan, explicit array \\
32 Software backends & CUDA compatibility backend and PRISM backend from shared Packet IR \\
33 \bottomrule
34 \end{longtable}

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