PRISM-1R

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32 \lhead{\small KOMOREBI PRISM-1R}
33 \rhead{\small Implementation and Deployment Blueprint v0.2}
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65 \begin{document}
66 
67 % -----------------------------------------------------------------------------
68 % COVER
69 % -----------------------------------------------------------------------------
70 \thispagestyle{empty}
71 \vspace*{0.55in}
72 \begin{center}
73 {\Huge\bfseries PRISM-1R}\\[0.12in]
74 {\LARGE\bfseries Implementation and Deployment Blueprint v0.2}\\[0.18in]
75 {\large Packet-programmable mixed-representation accelerator}\\[0.05in]
76 {\large Transformation plane + resolution plane + certificate-gated commit}\\[0.45in]
77 
78 \rule{0.90\linewidth}{0.8pt}\\[0.28in]
79 
80 \begin{tabularx}{0.88\linewidth}{>{\bfseries}p{1.55in}X}
81 Baseline & PRISM-1 Final Updated architecture specification \\
82 Revision & PRISM-1R physicalization and deployment blueprint \\
83 Deployment target & Golden model $\rightarrow$ CUDA $\rightarrow$ cycle simulator $\rightarrow$ FPGA $\rightarrow$ shuttle chiplet $\rightarrow$ reference chiplet $\rightarrow$ full package \\
84 Primary rule & Preserve structure. Execute locally. Refine only where evidence requires it. \\
85 Status & Engineering blueprint. Not fabricated silicon. All frequency, bandwidth, area and power values remain design targets until measured. \\
86 \end{tabularx}
87 
88 \vfill
89 {\large Komorebi P.}\par
90 \vspace{0.08in}
91 {\small Implementation handoff draft v0.2}\par
92 \end{center}
93 \newpage
94 
95 \tableofcontents
96 \newpage
97 
98 % -----------------------------------------------------------------------------
99 \section{Purpose and Deployment Philosophy}
100 
101 PRISM-1R converts the existing PRISM architecture into an implementation program. The objective is not to freeze every circuit choice prematurely. The objective is to freeze the \emph{semantic contracts} that software, simulation, FPGA and ASIC implementations must share, while keeping physical parameters adjustable until measurement and synthesis justify them.
102 
103 The architecture is organized around one principle:
104 \[
105 \boxed{\text{Do not materialize, move, or schedule structure already declared inactive.}}
106 \]
107 
108 PRISM-1R adds a second principle:
109 \[
110 \boxed{\text{Do not execute at a resolution that current evidence has already invalidated.}}
111 \]
112 
113 The machine therefore chooses four quantities jointly:
114 \[
115 \boxed{(\text{representation},\ \text{resolution},\ \text{placement},\ \text{precision}).}
116 \]
117 
118 A dense tensor remains a legal representation and fallback. It is not privileged as mandatory machine state.
119 
120 \statusbox{Scope boundary.}{This document specifies interfaces, resource organization, deployment stages, verification obligations, prototype gates, and operating procedures. It does not claim completed production RTL, timing closure, physical signoff, fabricated silicon performance, or measured package power.}
121 
122 % -----------------------------------------------------------------------------
123 \section{Reference Configuration}
124 
125 The reference package preserves the broad PRISM-1 scale while revising locality and control organization.
126 
127 \begin{table}[h]
128 \centering
129 \caption{PRISM-1R reference targets. Values are design targets, not measured silicon.}
130 \begin{tabularx}{0.96\linewidth}{Xr}
131 \toprule
132 \textbf{Resource} & \textbf{Reference target}\\
133 \midrule
134 Compute chiplets & 4\\
135 Packet Streaming Multiprocessors (PSMs) & 64 total\\
136 PSMs per chiplet & 16\\
137 Quadrants per chiplet & 4\\
138 Execution groups & 256 total\\
139 Execution groups per PSM & 4\\
140 Matrix array per execution group & $16\times16$\\
141 Clock modeling point & 1.5 GHz\\
142 Scratchpad per PSM & 2 MiB\\
143 Physical scratchpad banks & 16 $\times$ 128 KiB\\
144 Shared SRAM per chiplet & 16 MiB\\
145 Total local + shared SRAM & 192 MiB\\
146 Transform engines & 32 total\\
147 Small-solver engines & 16 total\\
148 Exact arithmetic clusters & 4 total\\
149 HBM4 stacks & 4\\
150 Reference HBM capacity & 144 GiB total\\
151 Reference aggregate HBM bandwidth & $>11.2$ TB/s\\
152 Package link class & UCIe 3.0 class\\
153 Host link class & PCIe 7.0 x16 class, optional CXL\\
154 Reference package power envelope & 500 W\\
155 \bottomrule
156 \end{tabularx}
157 \end{table}
158 
159 Dense peak remains secondary. The architecture succeeds only when mathematical structure removes enough arithmetic, storage, synchronization, or movement to justify specialized execution.
160 
161 % -----------------------------------------------------------------------------
162 \section{Python-Generated Architecture Blueprint}
163 
164 The following blueprint is generated programmatically from the same reference parameters used by this deployment guide. The figure is intended to function as an implementation map rather than a presentation illustration.
165 
166 \begin{landscape}
167 \thispagestyle{empty}
168 \begin{center}
169 \includegraphics[width=0.985\linewidth]{../figures/PRISM-1R_Python_Architecture_Blueprint.pdf}
170 \end{center}
171 \end{landscape}
172 
173 % -----------------------------------------------------------------------------
174 \section{What Must Be Frozen Before Production RTL}
175 
176 Freeze semantics before circuit details. A production RTL effort should not begin until the following objects have versioned, testable definitions.
177 
178 \begin{enumerate}
179 \item Packet descriptor semantics.
180 \item Transfer-edge descriptor semantics.
181 \item Atlas and selector semantics.
182 \item Refinement-family and parent/child semantics.
183 \item Representation and output-contract semantics.
184 \item Dependency token and completion token semantics.
185 \item Generation-number invalidation semantics.
186 \item Precision, sensitivity, and error-budget semantics.
187 \item Certificate acceptance semantics.
188 \item Commit, replay, and fault-containment semantics.
189 \item Command-buffer ABI and completion-record ABI.
190 \item Packet IR canonical serialization.
191 \item CUDA/PRISM backend conformance requirements.
192 \end{enumerate}
193 
194 The following should remain parameterized until synthesis, FPGA measurement, or floorplanning provides evidence: scratchpad port width, final SRAM macro organization, issue width, exact NoC link width, number of virtual channels beyond the minimum classes, DVFS domains, exact root-solver microarchitecture, and hardened interface IP choices.
195 
196 % -----------------------------------------------------------------------------
197 \section{Dual-Plane Execution Model}
198 
199 PRISM-1R separates two control problems that were previously too implicit.
200 
201 \subsection{Transformation plane}
202 
203 The transformation plane performs computation within the current representation and resolution:
204 \[
205 P_\alpha x \longmapsto P_\beta T P_\alpha x.
206 \]
207 
208 Typical operations include block matrix products, low-rank contractions, transform stages, Kronecker mode products, sparse-chain applications, modular operations, nonlinear memory kernels, reductions, and small solves.
209 
210 \subsection{Resolution plane}
211 
212 The resolution plane modifies the decomposition itself:
213 \[
214 P_\alpha \longleftrightarrow \{P_{\alpha_1},\ldots,P_{\alpha_k}\}.
215 \]
216 
217 It handles split, coarsen, local refinement, atlas changes, reconstruction changes, and replay boundaries.
218 
219 \subsection{Generation guard}
220 
221 Each mutable packet family carries a generation number $g$. A command records the generation it consumed. Refinement increments $g$ for the affected family. A provisional result may commit only if
222 \[
223 \boxed{g_{\rm consumed}=g_{\rm current}.}
224 \]
225 
226 This mechanism converts stale work after adaptive refinement into an explicit hardware predicate rather than a software convention.
227 
228 % -----------------------------------------------------------------------------
229 \section{Packet Streaming Multiprocessor Blueprint}
230 
231 One PSM is the independently scheduled execution unit. The recommended block composition is:
232 
233 \begin{lstlisting}
234 Packet front end
235   -> dependency / generation scoreboard
236   -> representation router -----------+
237   -> resolution controller -----------|--- adaptive control
238                                       |
239 16-bank 2 MiB scratchpad <------------+
240   -> EG0: 16x16 MMA + vector
241   -> EG1: 16x16 MMA + vector
242   -> EG2: 16x16 MMA + vector
243   -> EG3: 16x16 MMA + vector
244   -> projector / polyphase DMA
245   -> transform port
246   -> solver port
247   -> local reduction fabric
248   -> residual / certificate accumulator
249   -> commit / replay controller
250 \end{lstlisting}
251 
252 \begin{figure}[ht]
253 \centering
254 \includegraphics[width=0.98\linewidth]{../figures/02_psm_microarchitecture.pdf}
255 \caption{Implementation-oriented PSM microarchitecture. The transformation plane executes within the current decomposition; the resolution plane changes that decomposition and can trigger bounded replay.}
256 \end{figure}
257 
258 Each execution group is intentionally modest. The PSM is not designed to maximize unstructured GEMM density. It is designed to keep the selected representation resident and avoid repeated conversion into a generic dense form.
259 
260 \subsection{Command state machine}
261 
262 A minimal command lifecycle is
263 \[
264 \texttt{QUEUED}
265 \rightarrow \texttt{READY}
266 \rightarrow \texttt{DISPATCHED}
267 \rightarrow \texttt{PROVISIONAL}
268 \rightarrow \texttt{CERTIFIED}
269 \rightarrow \texttt{COMMITTED}.
270 \]
271 
272 Failure paths are explicit:
273 \[
274 \texttt{PROVISIONAL}\rightarrow \texttt{REFINE}\rightarrow\texttt{REPLAY}
275 \]
276 or
277 \[
278 \texttt{PROVISIONAL}\rightarrow \texttt{ABORT}.
279 \]
280 
281 Kernel completion and architectural visibility are therefore different events.
282 
283 % -----------------------------------------------------------------------------
284 \section{Scratchpad and Memory System}
285 
286 \subsection{PSM scratchpad}
287 
288 Keep the 2 MiB capacity but replace the vague four-bank concept with 16 physical banks:
289 \[
290 16\times128\text{ KiB}=2\text{ MiB}.
291 \]
292 
293 Retain four logical allocator classes:
294 
295 \begin{table}[h]
296 \centering
297 \begin{tabularx}{0.94\linewidth}{>{\bfseries}p{0.55in}p{1.6in}X}
298 \toprule
299 Class & Name & Typical contents\\
300 \midrule
301 P & Packet region & active blocks, packet outputs, local destination accumulators\\
302 F & Factor region & low-rank factors, transform stages, Kronecker factors, solver panels\\
303 M & Metadata region & descriptors, selectors, indices, dependency state, compact graph records\\
304 R & Residual region & residuals, norms, certificate state, replay records, refinement summaries\\
305 \bottomrule
306 \end{tabularx}
307 \end{table}
308 
309 The classes are compiler-visible pools, not rigid physical partitions.
310 
311 \subsection{Bandwidth modeling point}
312 
313 If each of 16 banks supplies a 256-bit word per cycle, the aggregate raw bandwidth is
314 \[
315 16\times 32\text{ B/cycle}=512\text{ B/cycle}.
316 \]
317 At 1.5 GHz this is
318 \[
319 \boxed{768\text{ GB/s per PSM raw scratchpad bandwidth}.}
320 \]
321 
322 A simple FP16 feed estimate for one $16\times16$ array is 32 FP16 operands per active cycle, or 64 B/cycle. Four execution groups therefore require roughly
323 \[
324 4\times64=256\text{ B/cycle}
325 \]
326 for direct operand feed before output traffic and reuse effects, corresponding to approximately 384 GB/s at 1.5 GHz. The proposed bank organization therefore begins with roughly 2x raw headroom against that simplified feed estimate. This is a modeling target, not a timing guarantee.
327 
328 \subsection{Hierarchy}
329 
330 \begin{itemize}
331 \item HBM: exact archive, cold factors, large graphs, model history, oversized packets.
332 \item Chiplet shared SRAM: active packet graph, hot immutable factors, cross-PSM transform state.
333 \item PSM scratchpad: active tiles, factors, solver panels, residuals, local metadata.
334 \item Registers / array state: immediate execution state.
335 \end{itemize}
336 
337 % -----------------------------------------------------------------------------
338 \section{Chiplet Quadrant Organization}
339 
340 A compute chiplet is divided into four locality quadrants. Each quadrant contains:
341 \[
342 \boxed{4\text{ PSMs}+4\text{ MiB shared SRAM}+2\text{ transform engines}+1\text{ solver}.}
343 \]
344 
345 This exactly consumes the chiplet-level reference resources while reducing the distance between packet execution, transform stages, and small solves.
346 
347 The placement objective is not merely minimum latency. It is minimum structured movement:
348 \[
349 \min \sum_{e\in E} \operatorname{bytes}(e)\times\operatorname{hops}(e).
350 \]
351 
352 Hot factors should be replicated read-only where the replication cost is lower than repeated network movement. Mutable packet state should retain clear ownership.
353 
354 % -----------------------------------------------------------------------------
355 \section{Network-on-Chip Blueprint}
356 
357 PRISM-1R uses separate logical control and payload service, even if an implementation shares physical wires.
358 
359 \begin{table}[h]
360 \centering
361 \caption{Minimum traffic classes.}
362 \begin{tabularx}{0.97\linewidth}{p{0.55in}p{1.55in}X X}
363 \toprule
364 \textbf{Class} & \textbf{Traffic} & \textbf{Service rule} & \textbf{Examples}\\
365 \midrule
366 C0 & commit / fault & forward-progress guaranteed & certificate acceptance, dependency wakeup, invalidation, exception\\
367 C1 & metadata & latency-oriented & descriptors, compact graph state, selector records\\
368 C2 & payload & bandwidth-oriented & blocks, factors, transform streams, packet transfers\\
369 C3 & reduction & bounded service & residual summaries, tree reductions, reconstruction contributions\\
370 \bottomrule
371 \end{tabularx}
372 \end{table}
373 
374 C2 saturation must never prevent C0 progress. This is a correctness requirement, not only a performance preference.
375 
376 \begin{figure}[ht]
377 \centering
378 \includegraphics[width=0.91\linewidth]{../figures/03_chiplet_noc_locality.pdf}
379 \caption{Chiplet locality and NoC organization. Quadrant locality is the default placement unit, while cross-quadrant traffic remains explicit and measurable.}
380 \end{figure}
381 
382 An initial packet-link modeling point is 1024 bits at 1.5 GHz:
383 \[
384 128\text{ B/cycle}\times1.5\text{ GHz}=\boxed{192\text{ GB/s per unidirectional link}}
385 \]
386 before encoding, arbitration, flow control, ECC, and protocol overhead.
387 
388 \subsection{Residency states}
389 
390 Avoid a CPU-style general coherence protocol. Use three architectural residency states:
391 
392 \begin{description}[leftmargin=1.25in,style=nextline]
393 \item[owned] one location may mutate the packet or representation state;
394 \item[replicated-read] immutable factors, atlas data, or descriptors may exist at multiple locations;
395 \item[streaming] the payload has no persistent residency and is consumed in flight.
396 \end{description}
397 
398 Generation invalidation handles stale read replicas associated with refinement.
399 
400 % -----------------------------------------------------------------------------
401 \section{Certificate, Commit, and Replay}
402 
403 Certification is a first-class data path. A kernel result is provisional until its declared acceptance rule passes.
404 
405 \subsection{Fused accumulation}
406 
407 Do not implement certification as a second full read of the result. Execution should tap quantities such as residual components, norms, energy partitions, trace summaries, rank margins, rounding bounds, and branch margins while the producing data is already live.
408 
409 \subsection{Hierarchical aggregation}
410 
411 Use the hierarchy
412 \[
413 \text{execution group}\rightarrow\text{PSM}\rightarrow\text{quadrant}\rightarrow\text{chiplet}\rightarrow\text{exact cluster when required}.
414 \]
415 
416 For example, local squared residual summaries may reduce as
417 \[
418 R_P^2=\sum_i r_i^2
419 \]
420 without transmitting the original packet tensor through the certificate network.
421 
422 \subsection{Commit predicate}
423 
424 A provisional result commits only if all required conditions hold:
425 \[
426 \boxed{
427 \texttt{CERT\_PASS}
428 \land
429 \texttt{GEN\_CURRENT}
430 \land
431 \texttt{NO\_UNCORRECTABLE\_FAULT}
432 \land
433 \texttt{DEPENDENCIES\_VALID}.
434 }
435 \]
436 
437 A failure should invalidate the smallest declared replay region unless the error is explicitly package-wide.
438 
439 \begin{figure}[ht]
440 \centering
441 \includegraphics[width=0.96\linewidth]{../figures/04_commit_refinement_state_machine.pdf}
442 \caption{Command and commit state machine. The key safety property is that no direct path exists from a provisional result to committed state without the declared certificate and generation checks.}
443 \end{figure}
444 
445 % -----------------------------------------------------------------------------
446 \section{Packet IR, Compiler, and Runtime Contract}
447 
448 Packet IR is the stable software/hardware boundary. CUDA and PRISM backends consume the same typed graph and must preserve the same mathematical output contract.
449 
450 \subsection{Planner objective}
451 
452 The PRISM-1R planner should minimize a physicalized cost rather than arithmetic alone:
453 \[
454 C(G)=
455 \alpha F
456 +\beta B_{\rm HBM}
457 +\gamma B_{\rm SRAM}
458 +\delta H_{\rm NoC}
459 +\eta L_{\rm sync}
460 +\kappa C_{\rm cert}
461 +\rho\,\mathbb E[C_{\rm replay}].
462 \]
463 
464 Here $F$ is arithmetic work, $B_{\rm HBM}$ and $B_{\rm SRAM}$ are bytes moved at each level, $H_{\rm NoC}$ is hop-bytes, $L_{\rm sync}$ is synchronization cost, $C_{\rm cert}$ is certificate cost, and the final term accounts for expected replay after adaptive refinement.
465 
466 A decomposition is not beneficial merely because it has a structured name. The compiler must include a generic fallback leaf and negative controls.
467 
468 \subsection{Software layers}
469 
470 \begin{enumerate}
471 \item Mathematical reference kernels and conformance vectors.
472 \item Packet IR builder, validator, serializer, and graph visualizer.
473 \item Representation/resolution/placement/precision planner.
474 \item CUDA packet backend.
475 \item PRISM functional simulator.
476 \item PRISM cycle-aware simulator.
477 \item Runtime queues, allocator, residency manager, telemetry, and driver interface.
478 \item FPGA firmware and hardware driver.
479 \item ASIC firmware and package runtime.
480 \end{enumerate}
481 
482 % -----------------------------------------------------------------------------
483 \section{Command and Descriptor ABI}
484 
485 Use a fixed command envelope with versioned payload schemas. Opcode semantics should remain stable across CUDA emulation, simulator, FPGA, and ASIC.
486 
487 \subsection{Candidate 256-bit Packet Seed Command envelope}
488 
489 The following packing is a \emph{prototype ABI candidate}, not a frozen physical bit allocation. Its purpose is to prove that command identity, dependency identity, generation identity, and certificate identity fit comfortably in a compact fixed-width envelope.
490 
491 \begin{table}[ht]
492 \centering
493 \caption{Candidate Packet Seed Command fields.}
494 \begin{tabularx}{0.96\linewidth}{p{1.45in}rX}
495 \toprule
496 \textbf{Field} & \textbf{Bits} & \textbf{Role}\\
497 \midrule
498 opcode & 8 & operation family\\
499 flags & 8 & deterministic mode, replay policy, privilege and compact modifiers\\
500 ABI version & 8 & command compatibility guard\\
501 format & 8 & arithmetic / payload format class\\
502 packet ID & 32 & primary packet identity\\
503 source descriptor & 32 & source descriptor-table index or handle\\
504 destination descriptor & 32 & destination descriptor-table index or handle\\
505 dependency token & 24 & readiness / wakeup dependency\\
506 generation & 24 & consumed packet-family generation\\
507 certificate ID & 24 & acceptance-rule record\\
508 payload or immediate & 56 & compact immediate, pointer fragment, shape class, or opcode-specific payload\\
509 \midrule
510 Total & 256 & fixed command envelope\\
511 \bottomrule
512 \end{tabularx}
513 \end{table}
514 
515 \begin{figure}[ht]
516 \centering
517 \includegraphics[width=0.98\linewidth]{../figures/06_command_envelope.pdf}
518 \caption{Proposed 256-bit command envelope. Semantic fields should freeze before the final bit positions do.}
519 \end{figure}
520 
521 \subsection{Candidate packet descriptor packing}
522 
523 A first 256-bit packet descriptor can carry the following information without external expansion for common cases:
524 
525 \begin{center}
526 \begin{tabular}{lr}
527 \toprule
528 packet ID / parent ID & $32+32$ bits\\
529 atlas ID / selector ID & $24+24$ bits\\
530 shape dimensions 0 and 1 & $16+16$ bits\\
531 location or compact pointer & 32 bits\\
532 precision / error-budget class & $8+8$ bits\\
533 generation & 24 bits\\
534 flags & 16 bits\\
535 reserved / extension class & 24 bits\\
536 \midrule
537 Total & 256 bits\\
538 \bottomrule
539 \end{tabular}
540 \end{center}
541 
542 Larger ranks, higher-dimensional shapes, or wide pointers use extension records rather than silently changing the base record interpretation.
543 
544 \subsection{Minimum descriptor classes}
545 
546 \begin{itemize}
547 \item packet descriptor;
548 \item transfer-edge descriptor;
549 \item atlas descriptor;
550 \item refinement-family descriptor;
551 \item precision / sensitivity / error-budget record;
552 \item dependency and completion token;
553 \item generation record;
554 \item residency record;
555 \item completion record;
556 \item certificate record.
557 \end{itemize}
558 
559 \subsection{Minimum first-generation commands}
560 
561 {\small\begin{longtable}{p{1.45in}p{5.05in}}
562 \toprule
563 \textbf{Command} & \textbf{Meaning}\\
564 \midrule
565 \endfirsthead
566 \toprule
567 \textbf{Command} & \textbf{Meaning}\\
568 \midrule
569 \endhead
570 \code{PSELECT} & apply a packet selector without materializing a dense projector\\
571 \code{PSPLIT} & replace a parent packet with a declared child family\\
572 \code{PCOARSEN} & reconstruct a parent from a complete child family\\
573 \code{POLYPHASE} & extract, permute, or interleave residue / phase channels\\
574 \code{WAVELET\_LIFT} & execute lifting predict/update/scale stages\\
575 \code{BLK\_GEMM} & execute equal-shape block transfer batches\\
576 \code{BDLR\_APPLY} & apply block-diagonal-plus-low-rank form without dense materialization\\
577 \code{HANKEL\_BUILD} & stream moment packets into a compact Hankel system\\
578 \code{ROOT\_PHASE} & perform small root / phase recovery sequence\\
579 \code{GRAPH\_REFINE} & replace one parent task with a local child graph\\
580 \code{RESIDUAL} & form / accumulate a declared reconstruction residual\\
581 \code{COMMIT} & publish a provisional result after certificate and generation checks\\
582 \code{GENERIC} & execute a non-specialized compatibility leaf\\
583 \bottomrule
584 \end{longtable}
585 
586 % -----------------------------------------------------------------------------
587 \section{Deployment Ladder and Exit Gates}
588 
589 \begin{figure}[ht]
590 \centering
591 \includegraphics[width=0.98\linewidth]{../figures/05_deployment_ladder.pdf}
592 \caption{Deployment ladder. Each stage exists to remove a different class of uncertainty before more expensive hardware is attempted.}
593 \end{figure}
594 
595 No stage advances because later hardware is attractive. It advances only when the preceding stage proves the contracts and exposes a measurable reason to continue.
596 
597 {\footnotesize\begin{longtable}{p{0.32in}p{0.92in}p{1.50in}p{1.88in}p{1.23in}}
598 \toprule
599 \textbf{Stage} & \textbf{Artifact} & \textbf{Purpose} & \textbf{Exit gate} & \textbf{Stop condition}\\
600 \midrule
601 \endfirsthead
602 \toprule
603 \textbf{Stage} & \textbf{Artifact} & \textbf{Purpose} & \textbf{Exit gate} & \textbf{Stop condition}\\
604 \midrule
605 \endhead
606 0 & Golden model & Freeze Packet IR semantics, reference kernels, certificates, replay, deterministic traces & All reference vectors pass; no ambiguous descriptor semantics & semantic mismatch\\
607 1 & CUDA packet backend & Prove the calculus runs on existing hardware and establish realistic baselines & Structured routes reduce bytes, work, or end-to-end cost on declared workload classes & only naming structure, no real reduction\\
608 2 & Cycle simulator & Model banks, queueing, NoC, contention, solver / transform occupancy, replay & No deadlock; calibrated bottleneck model; C0 forward progress under C2 saturation & model cannot reproduce measured microbenchmarks\\
609 3 & FPGA PSM & Measure command path, DMA, bank conflicts, generation guard, certificates, local replay & ABI conformance and measured execution of representative packet graphs & semantics change to fit FPGA\\
610 4 & Shuttle chiplet & Measure locality, hop-bytes, factor residency, transform-to-solver handoff & Stable same-representation advantage over optimized packet GPU for target classes & NoC / SRAM cost erases advantage\\
611 5 & Reference chiplet & Close chiplet timing, power, SRAM macros, network widths, DVFS & Full chiplet passes functional, timing, power and reliability gates & physical closure requires removing core semantics\\
612 6 & Full package & Validate multi-chiplet placement, HBM, package fabric, thermals and system software & Package-level performance and reliability goals achieved & package overhead dominates structured gain\\
613 \bottomrule
614 \end{longtable}
615 
616 % -----------------------------------------------------------------------------
617 \section{Stage 0: Golden Model}
618 
619 The golden model is the authoritative semantic implementation. It must be deliberately slow if necessary. Its purpose is correctness and traceability.
620 
621 Required outputs for every graph execution:
622 
623 \begin{itemize}
624 \item canonical Packet IR graph hash;
625 \item packet and transfer descriptors after validation;
626 \item chosen representation and resolution;
627 \item expected output contract;
628 \item arithmetic count and byte-count estimates;
629 \item dependency and generation trace;
630 \item provisional outputs;
631 \item certificate inputs and acceptance result;
632 \item replay/refinement events;
633 \item final committed outputs.
634 \end{itemize}
635 
636 The golden model should be the source of conformance vectors used by every later backend.
637 
638 % -----------------------------------------------------------------------------
639 \section{Stage 1: CUDA Packet Backend}
640 
641 The CUDA stage establishes the most important baseline: how far the representation itself can go before custom hardware contributes anything.
642 
643 Each experiment should separate:
644 \[
645 S_{\rm representation},\quad S_{\rm backend},\quad S_{\rm architecture},\quad S_{\rm amortized}.
646 \]
647 
648 Never report a combined ratio without preserving those components.
649 
650 Measure grouped block kernels, asynchronous transfers, factor residency, transform libraries, sparse kernels, Woodbury paths, packetwise mixed precision, graph replay, and negative controls.
651 
652 \statusbox{CUDA gate.}{Custom hardware is justified only for bottlenecks that remain after the packet representation is already implemented competently on an existing GPU.}
653 
654 % -----------------------------------------------------------------------------
655 \section{Stage 2: Cycle-Aware Simulator}
656 
657 The simulator must add physical constraints absent from the golden model:
658 
659 \begin{itemize}
660 \item 16-bank scratchpad conflicts and queueing;
661 \item execution-group issue / completion timing;
662 \item transform and solver contention;
663 \item C0-C3 network arbitration;
664 \item multicast and tree reductions;
665 \item shared-SRAM residency and eviction;
666 \item dependency wakeups;
667 \item certificate latency;
668 \item generation mismatch and local replay;
669 \item HBM request scheduling;
670 \item thermal / DVFS hooks for later calibration.
671 \end{itemize}
672 
673 The simulator should produce cycle-by-cycle counters and a summarized plan report. Do not silently hide bank conflicts or network queues inside an ``effective latency'' constant.
674 
675 % -----------------------------------------------------------------------------
676 \section{Stage 3: FPGA PSM Blueprint}
677 
678 The first FPGA target implements one logical PSM. Resource scaling is permitted, semantic scaling is not.
679 
680 \subsection{Required blocks}
681 
682 \begin{itemize}
683 \item command queue and descriptor fetch;
684 \item dependency + generation scoreboard;
685 \item 16-bank or proportionally banked BRAM/URAM scratchpad;
686 \item four logical execution groups or time-multiplexed equivalents;
687 \item projector/polyphase DMA path;
688 \item one transform path;
689 \item one small-solver path;
690 \item residual / certificate accumulator;
691 \item commit / replay controller;
692 \item performance-counter block;
693 \item fault injection for descriptor, generation, and certificate errors.
694 \end{itemize}
695 
696 \subsection{FPGA acceptance tests}
697 
698 \begin{enumerate}
699 \item Execute a block-diagonal workload without forming a dense matrix.
700 \item Execute BDLR apply with resident factors.
701 \item Execute a transform $\rightarrow$ small solve $\rightarrow$ reconstruction chain without host round-trip.
702 \item Trigger a certificate failure and verify local replay.
703 \item Trigger a generation change while work is provisional and prove stale commit is impossible.
704 \item Saturate payload traffic and demonstrate forward progress of C0 commit/dependency traffic.
705 \item Compare all committed outputs with golden-model vectors.
706 \end{enumerate}
707 
708 % -----------------------------------------------------------------------------
709 \section{Stages 4-6: ASIC Development Path}
710 
711 \subsection{Stage 4: shuttle chiplet}
712 
713 Use 4-8 PSMs and at least two quadrants. The key measurements are not dense FLOP/s. Measure:
714 
715 \begin{itemize}
716 \item local versus remote packet access;
717 \item hop-byte distribution;
718 \item factor reuse per load;
719 \item transform-to-solver handoff latency;
720 \item solver occupancy;
721 \item refinement invalidation radius;
722 \item certificate bandwidth;
723 \item energy per committed output.
724 \end{itemize}
725 
726 \subsection{Stage 5: reference chiplet}
727 
728 Scale to 16 PSMs and four quadrants. Freeze SRAM macro organization, final physical NoC width, clock domains, DVFS, and floorplan only after evidence from synthesis and the shuttle-scale measurements.
729 
730 \subsection{Stage 6: full package}
731 
732 Integrate four compute chiplets, I/O/control die, HBM, UCIe-class package links, host I/O, system firmware, telemetry, fault containment, and thermal control. The full package is a final integration stage, not the first place to discover whether packet locality works.
733 
734 % -----------------------------------------------------------------------------
735 \section{Verification and Signoff Matrix}
736 
737 {\small\begin{longtable}{p{0.82in}p{2.00in}p{1.67in}p{1.65in}}
738 \toprule
739 \textbf{Domain} & \textbf{Obligation} & \textbf{Primary method} & \textbf{Pass condition}\\
740 \midrule
741 \endfirsthead
742 \toprule
743 \textbf{Domain} & \textbf{Obligation} & \textbf{Primary method} & \textbf{Pass condition}\\
744 \midrule
745 \endhead
746 Semantic & reconstruction, transform/synthesis identity, output contracts & golden model + property tests & no semantic mismatch\\
747 Control & dependency tokens, generation invalidation, replay boundary & formal assertions + randomized traces & no stale commit, no deadlock\\
748 Arithmetic & mixed precision, exact modes, rank/phase decisions & bit-accurate models & declared certificate bound satisfied\\
749 Memory & bank conflicts, allocation, ECC/parity, double buffering & cycle sim + FPGA counters & stress targets met\\
750 NoC & traffic classes, multicast, reduction, congestion & adversarial traffic tests & C0 forward progress, no protocol deadlock\\
751 Compiler & representation/resolution/placement decisions & differential testing on small graphs & plan never changes semantics\\
752 Reliability & malformed commands, corrupted descriptors, replay storms & fault injection & deterministic containment and reporting\\
753 Physical & timing, power, thermal, IR drop, CDC/reset & EDA signoff & all process/package limits satisfied\\
754 \bottomrule
755 \end{longtable}
756 
757 % -----------------------------------------------------------------------------
758 \section{Benchmark Suite and Required Metrics}
759 
760 Every benchmark report should expose at least the following quantities.
761 
762 \begin{table}[h]
763 \centering
764 \begin{tabularx}{0.96\linewidth}{p{1.6in}X}
765 \toprule
766 \textbf{Metric} & \textbf{Definition / purpose}\\
767 \midrule
768 Bytes eliminated & explicit-array route bytes divided by packet-route bytes\\
769 Work eliminated & dense/reference arithmetic divided by executed arithmetic\\
770 Packet occupancy & useful execution-group cycles divided by available cycles\\
771 Residency reuse & number of factor/atlas uses per memory load\\
772 NoC cost & hop-bytes and utilization by C0-C3 traffic class\\
773 Refinement locality & remote state invalidated per local refinement event\\
774 Certificate overhead & certificate cycles and bytes divided by total execution\\
775 Replay cost & useful work discarded or repeated after refinement\\
776 Energy & joules per committed output\\
777 Fallback quality & fraction of negative controls correctly routed away from specialization\\
778 \bottomrule
779 \end{tabularx}
780 \end{table}
781 
782 Representative workload families should include structured linear operators, BDLR, regular block sparse graphs, transform-domain operators, unknown-edge reconstruction, small-solver-heavy chains, packet Bayesian portfolios, exact modular/residue workloads, and deliberately unstructured negative controls.
783 
784 % -----------------------------------------------------------------------------
785 \section{Deployment Runbook}
786 
787 \begin{enumerate}
788 \item \textbf{Build.} Compile the reference kernels, Packet IR tools, planner, CUDA backend, simulator, firmware, driver, and target image from one tagged release.
789 \item \textbf{Conformance.} Run descriptor schema tests and golden vectors before allowing hardware execution.
790 \item \textbf{Discover.} Query target capabilities: ABI version, PSM count, bank topology, formats, transform/solver inventory, link width, and exact-mode support.
791 \item \textbf{Preload.} Place immutable hot atlases and factors where reuse is expected.
792 \item \textbf{Plan.} Compile representation, resolution, placement, precision, and certificate plan. Emit a human-readable plan report.
793 \item \textbf{Execute.} Submit versioned command buffers and record queue, bank, NoC, execution, certificate, and replay telemetry.
794 \item \textbf{Validate.} Compare committed outputs against exact expectations or reference tolerances. Never consume provisional outputs.
795 \item \textbf{Profile.} Attribute bottlenecks separately to HBM, scratchpad banks, NoC, transforms, solvers, certificates, or replay.
796 \item \textbf{Promote.} Make a specialized route default only after repeatable wins and passing negative controls.
797 \item \textbf{Regress.} Re-run the canonical benchmark and fault-injection suites for every compiler, firmware, RTL, or physical-parameter change.
798 \end{enumerate}
799 
800 % -----------------------------------------------------------------------------
801 \section{Failure Policy}
802 
803 The deployment process should fail visibly rather than convert uncertainty into optimistic defaults.
804 
805 \begin{table}[h]
806 \centering
807 \begin{tabularx}{0.96\linewidth}{p{1.8in}X}
808 \toprule
809 \textbf{Failure} & \textbf{Required response}\\
810 \midrule
811 Unknown descriptor version & reject before execution\\
812 Uncorrectable descriptor corruption & abort affected command and invalidate dependent provisional work\\
813 Generation mismatch & prevent commit; replay smallest declared region\\
814 Certificate failure & refine, increase precision, choose alternate representation, or abort according to policy\\
815 C0 starvation & architecture bug; test must fail\\
816 Planner chooses unsupported feature & lower to legal fallback or reject; never reinterpret silently\\
817 Negative control forced into specialization & compiler quality failure\\
818 Backend disagrees with golden semantics & release-blocking error\\
819 Timing/power closure requires semantic weakening & stop physical implementation and redesign rather than changing the contract silently\\
820 \bottomrule
821 \end{tabularx}
822 \end{table}
823 
824 % -----------------------------------------------------------------------------
825 \section{RTL Partition and Interface Blueprint}
826 
827 The first RTL release should be deliberately narrow. The objective is to make the safety and scheduling boundaries executable before attempting high-throughput kernels.
828 
829 \begin{lstlisting}
830 rtl/
831   include/
832     prism_types_pkg.sv
833   core/
834     prism_command_frontend.sv
835     prism_descriptor_cache.sv
836     prism_dependency_scoreboard.sv
837     prism_generation_guard.sv
838     prism_representation_router.sv
839     prism_resolution_controller.sv
840     prism_scratchpad_banks.sv
841     prism_eg_cluster.sv
842     prism_transform_port.sv
843     prism_solver_port.sv
844     prism_certificate_accumulator.sv
845     prism_commit_controller.sv
846     prism_psm_top.sv
847   noc/
848     prism_control_router.sv
849     prism_packet_router.sv
850     prism_multicast_unit.sv
851     prism_reduction_unit.sv
852   tb/
853     tb_commit_semantics.sv
854     tb_generation_race.sv
855     tb_c0_forward_progress.sv
856     tb_local_replay.sv
857 \end{lstlisting}
858 
859 The accompanying handoff package includes boundary skeletons for the generation guard, commit controller, a PSM top-level shell, and a smoke-test bench. These are semantic scaffolds, not production RTL.
860 
861 \subsection{Recommended ready/valid discipline}
862 
863 All command, descriptor, and data interfaces should use explicit backpressure. A sender may not infer acceptance from elapsed cycles. For every channel:
864 \[
865 \texttt{transfer}=\texttt{valid}\land\texttt{ready}.
866 \]
867 
868 Metadata and payload channels should carry a transaction identity sufficient to detect mismatched completion records in simulation and debug builds.
869 
870 % -----------------------------------------------------------------------------
871 \section{PSM Pipeline and Scheduling Contract}
872 
873 A practical first implementation can expose the following logical pipeline. Physical retiming may alter cycle counts but must preserve the boundaries.
874 
875 \begin{enumerate}
876 \item \textbf{Fetch}: read fixed-width command envelope.
877 \item \textbf{Validate}: check ABI, opcode, descriptor bounds, privilege, and basic format legality.
878 \item \textbf{Resolve}: fetch packet, transfer, generation, and certificate descriptors.
879 \item \textbf{Ready}: dependency scoreboard confirms all required inputs are eligible.
880 \item \textbf{Reserve}: allocate scratchpad destination, execution route, and completion entry.
881 \item \textbf{Execute}: issue transformation or resolution work to the chosen engine.
882 \item \textbf{Provisional completion}: capture output identity, bytes, cycles, residual summary, and consumed generation.
883 \item \textbf{Commit resolution}: certificate + generation + fault + dependency predicate chooses commit, replay, or abort.
884 \end{enumerate}
885 
886 The scheduler may overlap commands aggressively, but it may not elide stages 3, 7, or 8. Those stages carry the semantic obligations that distinguish completion from commitment.
887 
888 \subsection{Scoreboard entries}
889 
890 At minimum, an in-flight entry should retain command ID, packet ID, consumed generation, dependency token, destination reservation, certificate ID, replay-region ID, engine assignment, and current state. Debug builds should additionally retain timestamps for every state transition.
891 
892 % -----------------------------------------------------------------------------
893 \section{Scratchpad Bank Contract}
894 
895 The 16 physical banks should be exposed to the allocator through a bank-mapping function rather than a fixed contiguous modulo mapping. Polyphase and strided packet accesses can otherwise create systematic conflict patterns.
896 
897 A prototype mapping may use a configurable XOR swizzle,
898 \[
899 \operatorname{bank}(w)=
900 \bigl(w_{3:0}\oplus w_{7:4}\oplus h(P)\bigr)\bmod 16,
901 \]
902 where $w$ is the local word index and $h(P)$ is a four-bit packet/phase hash. This is an implementation policy, not part of the mathematical contract, and should be replaced if FPGA counters show worse behavior for target transforms.
903 
904 Bank arbitration must report conflicts to performance counters. The simulator and FPGA must agree on the definition of a bank-conflict cycle before architectural performance claims are made.
905 
906 % -----------------------------------------------------------------------------
907 \section{Formal Safety Invariants}
908 
909 The following properties should be encoded as assertions in the RTL and independently checked in the reference model.
910 
911 \begin{description}[leftmargin=1.35in,style=nextline]
912 \item[I1: stale-commit exclusion] If the consumed generation differs from the current generation, \texttt{commit} is false.
913 \item[I2: certificate gating] If a required certificate is unfinished or failed, \texttt{commit} is false.
914 \item[I3: fault containment] An uncorrectable protected-state fault cannot produce a committed result.
915 \item[I4: dependency validity] A completion token cannot release downstream committed work before the producing command commits.
916 \item[I5: replay locality] A retryable failure invalidates only the declared replay region and its dependent provisional descendants.
917 \item[I6: control forward progress] Under finite injection and a responsive destination, C0 traffic cannot be permanently starved by C2/C3 traffic.
918 \item[I7: deterministic mode] When deterministic mode is requested, reduction topology, rounding mode, and replay decisions are reproducible from the same command and state trace.
919 \item[I8: backend semantic equivalence] CUDA, golden-model, FPGA, and ASIC executions of the same legal Packet IR program satisfy the same declared output contract.
920 \end{description}
921 
922 For I1 the hardware-level implication is simply
923 \[
924 (g_{\rm consumed}\neq g_{\rm current})\Rightarrow \neg\texttt{commit}.
925 \]
926 The implementation package includes a minimal executable reference test for this invariant.
927 
928 % -----------------------------------------------------------------------------
929 \section{Boot, Discovery, and Runtime Bring-Up}
930 
931 A target should not accept general packet programs immediately after reset. Recommended bring-up order:
932 
933 \begin{enumerate}
934 \item reset all PSMs, queues, routers, certificate accumulators, and generation tables;
935 \item verify ROM / firmware image and ABI compatibility;
936 \item scrub or initialize descriptor SRAM and protected control memories;
937 \item enumerate PSM, transform, solver, exact-arithmetic, SRAM-bank, HBM, and link capabilities;
938 \item run a local self-test for scratchpad banks, command queue, generation guard, and commit controller;
939 \item run a cross-quadrant C0/C2 traffic smoke test;
940 \item publish the capability block to the host runtime;
941 \item accept only Packet IR plans whose required feature set is a subset of the discovered capabilities.
942 \end{enumerate}
943 
944 A failed generation-guard or commit-controller self-test is a hard device-disable condition. A failed transform or solver self-test may permit a degraded capability profile if the runtime can route those operations elsewhere without changing semantics.
945 
946 % -----------------------------------------------------------------------------
947 \section{Telemetry and Performance-Counter Minimum Set}
948 
949 Every PSM should expose counters sufficient to distinguish a poor mathematical plan from a poor hardware mapping. Minimum counters:
950 
951 \begin{itemize}
952 \item commands fetched, issued, completed, committed, replayed, and aborted;
953 \item cycles stalled on dependency, destination allocation, scratchpad banks, NoC, transform, solver, certificate, and HBM;
954 \item scratchpad bytes read/written by P/F/M/R logical class;
955 \item bank-conflict cycles by bank and access class;
956 \item NoC flits or bytes by C0-C3 class and hop count;
957 \item factor / atlas reuse count;
958 \item generation mismatch count;
959 \item certificate failure count by reason;
960 \item replayed cycles and bytes;
961 \item deterministic-mode invocations;
962 \item corrected and uncorrectable protected-state errors.
963 \end{itemize}
964 
965 The planner calibration loop should consume these counters directly rather than tuning against wall-clock time alone.
966 
967 % -----------------------------------------------------------------------------
968 \section{Implementation Handoff Package}
969 
970 The v0.2 package accompanies this PDF with:
971 
972 \begin{itemize}
973 \item Python-generated PDF, SVG, and PNG engineering blueprints;
974 \item the Python figure generator;
975 \item SystemVerilog semantic boundary skeletons for generation and commit logic;
976 \item a minimal Python semantic reference model;
977 \item executable smoke tests for valid commit, stale generation replay, and fatal-fault abort;
978 \item a manifest and status boundary distinguishing implemented scaffolding from future production RTL.
979 \end{itemize}
980 
981 The supplied Python semantic tests pass in the build environment. No SystemVerilog compiler was available in that environment, so the RTL skeleton is \emph{not} claimed to have passed HDL compilation or synthesis.
982 
983 % -----------------------------------------------------------------------------
984 \section{Architecture Freeze Checklist}
985 
986 A PRISM-1R implementation is ready to enter production RTL only when all items below are checked.
987 
988 \begin{enumerate}[label=$\square$]
989 \item Packet / transfer / atlas / refinement / generation descriptor schemas are versioned.
990 \item Packet IR canonical serialization is stable.
991 \item Output contracts are explicit and tested.
992 \item Commit and replay state machines are formally specified.
993 \item Generation invalidation rules are formally specified.
994 \item Minimum C0-C3 traffic guarantees are specified.
995 \item Scratchpad allocator contract and bank-conflict behavior are specified.
996 \item Supported arithmetic formats and rounding rules are fixed.
997 \item Exact arithmetic obligations are bounded and specified.
998 \item Transform and small-solver minimum operation set is fixed.
999 \item CUDA and PRISM conformance vectors pass.
1000 \item Golden model is reproducible from a tagged release.
1001 \item Cycle simulator reports all modeled queues and conflicts.
1002 \item FPGA prototype demonstrates stale-commit prevention.
1003 \item FPGA prototype demonstrates certificate-triggered local replay.
1004 \item Negative controls route correctly.
1005 \item Benchmark reports separate representation, backend, architecture, and amortized effects.
1006 \item Fault-injection suite passes.
1007 \end{enumerate}
1008 
1009 % -----------------------------------------------------------------------------
1010 \section{First 30 Engineering Tasks}
1011 
1012 {\small\begin{longtable}{r p{6.15in}}
1013 \toprule
1014 \textbf{No.} & \textbf{Task}\\
1015 \midrule
1016 \endfirsthead
1017 \toprule
1018 \textbf{No.} & \textbf{Task}\\
1019 \midrule
1020 \endhead
1021 1 & Freeze Packet IR schema version 1.\\
1022 2 & Freeze packet, transfer, atlas, refinement, generation, and certificate descriptors.\\
1023 3 & Implement canonical binary/JSON serialization and schema validator.\\
1024 4 & Build deterministic golden Packet IR interpreter.\\
1025 5 & Define canonical execution trace format.\\
1026 6 & Implement generation guard in golden model.\\
1027 7 & Implement certificate state machine in golden model.\\
1028 8 & Implement local replay region semantics.\\
1029 9 & Port representative block-diagonal and BDLR graphs to canonical Packet IR.\\
1030 10 & Port transform-to-small-solver reconstruction chain.\\
1031 11 & Implement CUDA grouped block backend.\\
1032 12 & Implement CUDA factor-resident BDLR backend.\\
1033 13 & Implement CUDA transform/solver chain with graph replay.\\
1034 14 & Add structured and unstructured negative controls.\\
1035 15 & Define benchmark result schema separating gain types.\\
1036 16 & Implement PSM functional simulator.\\
1037 17 & Add 16-bank scratchpad timing model.\\
1038 18 & Add C0-C3 NoC queue model.\\
1039 19 & Add quadrant placement and hop-byte accounting.\\
1040 20 & Add transform/solver occupancy model.\\
1041 21 & Add hierarchical certificate timing model.\\
1042 22 & Add replay-cost estimator.\\
1043 23 & Implement joint representation/resolution/placement cost planner.\\
1044 24 & Write SystemVerilog command and descriptor interfaces.\\
1045 25 & Implement FPGA scoreboard and generation guard.\\
1046 26 & Implement FPGA scratchpad bank controller.\\
1047 27 & Implement FPGA certificate/commit path.\\
1048 28 & Implement fault injection and stale-generation testbench.\\
1049 29 & Run first end-to-end FPGA conformance workload.\\
1050 30 & Freeze shuttle-chiplet experiment matrix from measured FPGA bottlenecks.\\
1051 \bottomrule
1052 \end{longtable}
1053 
1054 % -----------------------------------------------------------------------------
1055 \section{Final Deployment Rule}
1056 
1057 The deployment program should preserve one strict ordering:
1058 \[
1059 \boxed{
1060 \text{mathematical contract}
1061 \rightarrow
1062 \text{software proof of execution}
1063 \rightarrow
1064 \text{measured bottleneck}
1065 \rightarrow
1066 \text{hardware specialization}.
1067 }
1068 \]
1069 
1070 PRISM-1R is justified only where the representation has already removed unnecessary work and where dedicated hardware measurably improves the remaining structured computation.
1071 
1072 The target machine is therefore not a GPU with extra packet opcodes. It is a processor in which representation, resolution, locality, uncertainty, and commit state are all architectural information.
1073 
1074 \vfill
1075 \begin{center}
1076 \rule{0.8\linewidth}{0.5pt}\\[0.08in]
1077 \small End of PRISM-1R Implementation and Deployment Blueprint v0.2
1078 \end{center}
1079 
1080 \end{document}

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