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$\\rightarrow$ full package \\\\\nPrimary rule & Preserve structure. Execute locally. Refine only where evidence requires it. \\\\\nStatus & Engineering blueprint. Not fabricated silicon. All frequency, bandwidth, area and power values remain design targets until measured. \\\\\n\\end{tabularx}\n\n\\vfill\n{\\large Komorebi P.}\\par\n\\vspace{0.08in}\n{\\small Implementation handoff draft v0.2}\\par\n\\end{center}\n\\newpage\n\n\\tableofcontents\n\\newpage\n\n% ---------------------------------------…","PRISM-1R adds a second principle:\n\\[\n\\boxed{\\text{Do not execute at a resolution that current evidence has already invalidated.}}\n\\]","The machine therefore chooses four quantities jointly:\n\\[\n\\boxed{(\\text{representation},\\ \\text{resolution},\\ \\text{placement},\\ \\text{precision}).}\n\\]","Matrix array per execution group & $16\\times16$","Physical scratchpad banks & 16 $\\times$ 128 KiB","Reference aggregate HBM bandwidth & $>11.2$ TB/s","The transformation plane performs computation within the current representation and resolution:\n\\[\nP_\\alpha x \\longmapsto P_\\beta T P_\\alpha x.\n\\]","The resolution plane modifies the decomposition itself:\n\\[\nP_\\alpha \\longleftrightarrow \\{P_{\\alpha_1},\\ldots,P_{\\alpha_k}\\}.\n\\]","Each mutable packet family carries a generation number $g$. A command records the generation it consumed. Refinement increments $g$ for the affected family. A provisional result may commit only if\n\\[\n\\boxed{g_{\\rm consumed}=g_{\\rm current}.}\n\\]","A minimal command lifecycle is\n\\[\n\\texttt{QUEUED}\n\\rightarrow \\texttt{READY}\n\\rightarrow \\texttt{DISPATCHED}\n\\rightarrow \\texttt{PROVISIONAL}\n\\rightarrow \\texttt{CERTIFIED}\n\\rightarrow \\texttt{COMMITTED}.\n\\]","Failure paths are explicit:\n\\[\n\\texttt{PROVISIONAL}\\rightarrow \\texttt{REFINE}\\rightarrow\\texttt{REPLAY}\n\\]\nor\n\\[\n\\texttt{PROVISIONAL}\\rightarrow \\texttt{ABORT}.\n\\]","Keep the 2 MiB capacity but replace the vague four-bank concept with 16 physical banks:\n\\[\n16\\times128\\text{ KiB}=2\\text{ MiB}.\n\\]","If each of 16 banks supplies a 256-bit word per cycle, the aggregate raw bandwidth is\n\\[\n16\\times 32\\text{ B/cycle}=512\\text{ B/cycle}.\n\\]\nAt 1.5 GHz this is\n\\[\n\\boxed{768\\text{ GB/s per PSM raw scratchpad bandwidth}.}\n\\]","A simple FP16 feed estimate for one $16\\times16$ array is 32 FP16 operands per active cycle, or 64 B/cycle. Four execution groups therefore require roughly\n\\[\n4\\times64=256\\text{ B/cycle}\n\\]\nfor direct operand feed before output traffic and reuse effects, corresponding to approximately 384 GB/s at 1.5 GHz. The proposed bank organization therefore begins with roughly 2x raw headroom against that simplified feed estimate. This is a modeling target, not a timing guarantee.","A compute chiplet is divided into four locality quadrants. Each quadrant contains:\n\\[\n\\boxed{4\\text{ PSMs}+4\\text{ MiB shared SRAM}+2\\text{ transform engines}+1\\text{ solver}.}\n\\]","The placement objective is not merely minimum latency. It is minimum structured movement:\n\\[\n\\min \\sum_{e\\in E} \\operatorname{bytes}(e)\\times\\operatorname{hops}(e).\n\\]","An initial packet-link modeling point is 1024 bits at 1.5 GHz:\n\\[\n128\\text{ B/cycle}\\times1.5\\text{ GHz}=\\boxed{192\\text{ GB/s per unidirectional link}}\n\\]\nbefore encoding, arbitration, flow control, ECC, and protocol overhead.","Use the hierarchy\n\\[\n\\text{execution group}\\rightarrow\\text{PSM}\\rightarrow\\text{quadrant}\\rightarrow\\text{chiplet}\\rightarrow\\text{exact cluster when required}.\n\\]","For example, local squared residual summaries may reduce as\n\\[\nR_P^2=\\sum_i r_i^2\n\\]\nwithout transmitting the original packet tensor through the certificate network.","A provisional result commits only if all required conditions hold:\n\\[\n\\boxed{\n\\texttt{CERT\\_PASS}\n\\land\n\\texttt{GEN\\_CURRENT}\n\\land\n\\texttt{NO\\_UNCORRECTABLE\\_FAULT}\n\\land\n\\texttt{DEPENDENCIES\\_VALID}.\n}\n\\]","The PRISM-1R planner should minimize a physicalized cost rather than arithmetic alone:\n\\[\nC(G)=\n\\alpha F\n+\\beta B_{\\rm HBM}\n+\\gamma B_{\\rm SRAM}\n+\\delta H_{\\rm NoC}\n+\\eta L_{\\rm sync}\n+\\kappa C_{\\rm cert}\n+\\rho\\,\\mathbb E[C_{\\rm replay}].\n\\]","Here $F$ is arithmetic work, $B_{\\rm HBM}$ and $B_{\\rm SRAM}$ are bytes moved at each level, $H_{\\rm NoC}$ is hop-bytes, $L_{\\rm sync}$ is synchronization cost, $C_{\\rm cert}$ is certificate cost, and the final term accounts for expected replay after adaptive refinement.","\\begin{center}\n\\begin{tabular}{lr}\n\\toprule\npacket ID / parent ID & $32+32$ bits","atlas ID / selector ID & $24+24$ bits","shape dimensions 0 and 1 & $16+16$ bits","precision / error-budget class & $8+8$ bits","Each experiment should separate:\n\\[\nS_{\\rm representation},\\quad S_{\\rm backend},\\quad S_{\\rm architecture},\\quad S_{\\rm amortized}.\n\\]","\\begin{enumerate}\n\\item Execute a block-diagonal workload without forming a dense matrix.\n\\item Execute BDLR apply with resident factors.\n\\item Execute a transform $\\rightarrow$ small solve $\\rightarrow$ reconstruction chain without host round-trip.\n\\item Trigger a certificate failure and verify local replay.\n\\item Trigger a generation change while work is provisional and prove stale commit is impossible.\n\\item Saturate payload traffic and demonstrate forward progress of C0 commit/dependency traffic.\n\\item Compare all committed outputs with golden-model vectors.\n\\end{enumerate}","All command, descriptor, and data interfaces should use explicit backpressure. A sender may not infer acceptance from elapsed cycles. For every channel:\n\\[\n\\texttt{transfer}=\\texttt{valid}\\land\\texttt{ready}.\n\\]","A prototype mapping may use a configurable XOR swizzle,\n\\[\n\\operatorname{bank}(w)=\n\\bigl(w_{3:0}\\oplus w_{7:4}\\oplus h(P)\\bigr)\\bmod 16,\n\\]\nwhere $w$ is the local word index and $h(P)$ is a four-bit packet/phase hash. This is an implementation policy, not part of the mathematical contract, and should be replaced if FPGA counters show worse behavior for target transforms.","For I1 the hardware-level implication is simply\n\\[\n(g_{\\rm consumed}\\neq g_{\\rm current})\\Rightarrow \\neg\\texttt{commit}.\n\\]\nThe implementation package includes a minimal executable reference test for this invariant.","\\begin{enumerate}[label=$\\square$]\n\\item Packet / transfer / atlas / refinement / generation descriptor schemas are versioned.\n\\item Packet IR canonical serialization is stable.\n\\item Output contracts are explicit and tested.\n\\item Commit and replay state machines are formally specified.\n\\item Generation invalidation rules are formally specified.\n\\item Minimum C0-C3 traffic guarantees are specified.\n\\item Scratchpad allocator contract and bank-conflict behavior are specified.\n\\item Supported arithmetic formats and rounding rules are fixed.\n\\item Exact arithmetic obligations are bounded and specified.\n\\item Transform and small-solver minimum operation set is fixed.\n\\item CUDA and PRISM conformance vectors pass.\n\\item Golden","The deployment program should preserve one strict ordering:\n\\[\n\\boxed{\n\\text{mathematical contract}\n\\rightarrow\n\\text{software proof of execution}\n\\rightarrow\n\\text{measured bottleneck}\n\\rightarrow\n\\text{hardware specialization}.\n}\n\\]"]}