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On the recorded RTX 3070 Ti Laptop GPU, an equal-block packet operator was measured at $0.046032$ ms and ran $14.8919\\times$ faster than its matched device-resident dense GPU row. A BDLR packet path with CUDA Graph replay was measured at $0.079872$ ms and ran $10.9355\\times$ faster than the matched dense GPU row. Graph replay improved the same packet representation by about $1.218\\times$. A compressed BDLR product took $0.1582$ ms, while materializing the output took $0.5073$ ms. These measurements show that the calculus can already execute on CUDA without preserving a dense matrix.","basis already exists. On the recorded RTX 3070 Ti Laptop GPU, an equal-block packet operator was measured at $0.046032$ ms and ran $14.8919\\times$ faster than its matched device-resident dense GPU row. A BDLR packet path with CUDA Graph replay was measured at $0.079872$ ms and ran $10.9355\\times$ faster than the matched dense GPU row. Graph replay improved the same packet representation by about $1.218\\times$. A compressed BDLR product took $0.1582$ ms, while materializing the output took $0.5073$ ms. These measurements show that the calculus can already execute on CUDA without preserving a dense matrix.","Ti Laptop GPU, an equal-block packet operator was measured at $0.046032$ ms and ran $14.8919\\times$ faster than its matched device-resident dense GPU row. A BDLR packet path with CUDA Graph replay was measured at $0.079872$ ms and ran $10.9355\\times$ faster than the matched dense GPU row. Graph replay improved the same packet representation by about $1.218\\times$. A compressed BDLR product took $0.1582$ ms, while materializing the output took $0.5073$ ms. These measurements show that the calculus can already execute on CUDA without preserving a dense matrix.","s measured at $0.046032$ ms and ran $14.8919\\times$ faster than its matched device-resident dense GPU row. A BDLR packet path with CUDA Graph replay was measured at $0.079872$ ms and ran $10.9355\\times$ faster than the matched dense GPU row. Graph replay improved the same packet representation by about $1.218\\times$. A compressed BDLR product took $0.1582$ ms, while materializing the output took $0.5073$ ms. These measurements show that the calculus can already execute on CUDA without preserving a dense matrix.","PRISM addresses the work left after the representation has already improved. Its likely advantages come from resident factor reuse, packet gather and scatter, transform-to-solver handoff, grouped small-block dispatch, local refinement, deterministic graph replay, and certificate accumulation. The architecture model estimates gains of $2.96\\times$ for the resident edge-recovery chain, $1.64\\times$ for a fused multi-atlas path, and $1.42\\times$ for a shape-batched Bayesian portfolio. Those are architecture estimates. They are not silicon measurements.","the representation has already improved. Its likely advantages come from resident factor reuse, packet gather and scatter, transform-to-solver handoff, grouped small-block dispatch, local refinement, deterministic graph replay, and certificate accumulation. The architecture model estimates gains of $2.96\\times$ for the resident edge-recovery chain, $1.64\\times$ for a fused multi-atlas path, and $1.42\\times$ for a shape-batched Bayesian portfolio. Those are architecture estimates. They are not silicon measurements.","The earlier $37.8\\times$ dense-route comparison is retained only as a total route model. It combines a better representation with a different architecture. It is not reported as a PRISM-over-CUDA architecture gain.","Projector-resolved computation starts before that flattening step. Let\n\\[\nX=\\bigoplus_{\\alpha\\in I}X_\\alpha,\n\\qquad\nP_\\alpha P_\\beta=\\delta_{\\alpha\\beta}P_\\alpha,\n\\qquad\n\\sum_{\\alpha\\in I}P_\\alpha=I.\n\\]\nFor an operator $T:X\\to X$, the native objects are the transfer blocks\n\\[\nT_{\\beta\\alpha}=P_\\beta T P_\\alpha.\n\\]\nThe complete operator is reconstructed by\n\\[\n\\boxed{T=\\sum_{\\alpha,\\beta}T_{\\beta\\alpha}.}\n\\]\nThe zero pattern, block shapes, rank structure, parent-child relations, and packet sensitivities are part of the problem. PRISM-1 carries them into the execution model instead of asking software to rediscover them after every kernel boundary.","\\section{No dense preservation requirement}\nThe architecture does not begin with a dense matrix and try to compress it after the fact. It begins with a typed operator. That operator may be represented as\n\\[\n\\boxed{\n\\begin{aligned}\n\\mathfrak R=\\{&\\text{explicit array},\\ \\text{block},\\ \\text{block sparse},\\ \\text{low rank},\\ \\text{BDLR},\\\\\n&\\text{Kronecker},\\ \\text{sparse chain},\\ \\text{transform plan},\\ \\text{packet graph}\\}.\n\\end{aligned}\n}\n\\]\nA dense representation is useful when no better form exists or when a downstream user explicitly asks for every entry. It is not a state that the chip must preserve.","\\section{CUDA-like execution hierarchy}\nCUDA made heterogeneous arithmetic programmable through a hierarchy of lanes, warps, blocks, grids, and memories. PRISM uses an analogous execution hierarchy while retaining the mathematical structure that CUDA kernels normally receive only through software conventions:\n\\[\n\\boxed{\n\\text{lane}\n\\longrightarrow\n\\text{packet warp}\n\\longrightarrow\n\\text{execution group}\n\\longrightarrow\n\\text{Packet Streaming Multiprocessor}\n\\longrightarrow\n\\text{packet graph}.\n}\n\\]\nA packet warp may invoke a matrix group, vector lanes, a transform engine, a small solver, exact arithmetic, or a memory operator. The representation router chooses the form declared by Packet IR. Several forms may appear in one graph.","\\section{Compatible middle bases}\nThe intermediate basis is part of the optimization. For any invertible $S$,\n\\[\nAB=(AS)(S^{-1}B).\n\\]\nSuppose\n\\[\nA=L D_A S^{-1},\n\\qquad\nB=S D_B R.\n\\]\nThen\n\\[\n\\boxed{AB=L(D_AD_B)R.}\n\\]\nWhen $L$, $S$, and $R$ have fast application and $D_A$, $D_B$ are block diagonal, the product inherits the blockwise cost plus the transform costs. Fourier diagonalization of circulants, simultaneous diagonalization, symmetry sectors, and tensor factorizations are instances of the same rule.","\\section{Sparse chains and transform plans}\nA matrix may be dense as an array and cheap as an operator. If\n\\[\nA=F_LF_{L-1}\\cdots F_1\n\\]\nand each factor has $O(n)$ nonzero entries, then applying $A$ costs $O(nL)$. If $L=O(\\log n)$, the cost is $O(n\\log n)$. FFT and butterfly operators fit this pattern. PRISM stores the factor chain and executes it. It does not store the dense array represented by the chain.","For a fixed candidate tree, each choice $o$ has a local cost $c(o)$, a local error $e(o)$, and zero or more children. The planner evaluates\n\\[\nJ(v)=\\min_{o\\in\\mathcal O_v}\n\\left[\n c(o)+\\lambda e(o)^2+\n \\sum_{u\\in\\operatorname{child}(o)}J(u)\n\\right].\n\\]\nBottom-up evaluation is globally optimal on the fixed tree because every feasible plan consists of one local choice followed by feasible child plans.","Execution group array & $16\\times16$ matrix array plus vector lanes","\\section{Compute-chiplet layout}\nThe reference chiplet places a $4\\times4$ mesh of Packet Streaming Multiprocessors at its center. Every multiprocessor contains four execution groups, giving 64 matrix and vector groups per chiplet. Transform engines sit along one edge, solver engines along another, shared SRAM banks line the data path, and the UCIe router occupies a package-facing edge. This is a planning floorplan rather than a placed design. Its purpose is to make communication and locality assumptions visible early.","\\section{Modeled arithmetic peaks}\nWith 256 execution groups and one $16\\times16$ matrix array per group, the model yields\n\\[\n\\boxed{\n\\begin{aligned}\n\\text{FP16 or BF16} &\\approx 196.6\\text{ TFLOP/s},","\\section{Modeled arithmetic peaks}\nWith 256 execution groups and one $16\\times16$ matrix array per group, the model yields\n\\[\n\\boxed{\n\\begin{aligned}\n\\text{FP16 or BF16} &\\approx 196.6\\text{ TFLOP/s},\\\\\n\\text{FP32} &\\approx 98.3\\text{ TFLOP/s},\\\\\n\\text{FP64} &\\approx 24.6\\text{ TFLOP/s}.\n\\end{aligned}}\n\\]\nThese are model peaks. The design is not organized around a claim of superior generic dense throughput. Its purpose is to execute fewer operations and move fewer bytes when the selected representation proves that the explicit array is unnecessary.","\\section{Execution groups}\nEach of the four execution groups contains a $16\\times16$ matrix array and programmable vector lanes. Equal-shape blocks can be grouped across execution groups. The same lanes handle low-rank contractions, Kronecker mode products, sparse-chain factors, selectors, reductions, index generation, and generic leaves.","\\begin{definition}[Packet descriptor]\nA packet descriptor is a typed record\n\\[\n\\mathsf P=(i,p,a,\\sigma,\\mathbf n,\\ell,\\pi,\\tau),\n\\]\nwhere $i$ is the packet ID, $p$ is the parent, $a$ is the atlas, $\\sigma$ is the selector type, $\\mathbf n$ is the shape, $\\ell$ is the storage location, $\\pi$ is the precision tag, and $\\tau$ is the allowed local error contribution.\n\\end{definition}","\\section{Transfer edge descriptor}\nThe transfer descriptor is the hardware form of $P_\\beta T P_\\alpha$. It identifies the source and destination packets, operator class, shape, rank, precision, sensitivity, payload, and dependency token.","\\section{Atlas descriptor}\nAn atlas descriptor records an analysis graph, a synthesis graph, normalization data, and packet selectors. A unitary transform uses its adjoint for synthesis. A redundant exact frame records the canonical dual or another declared synthesis map satisfying\n\\[\n\\Scal\\Acal=I.\n\\]","\\section{Representation-first storage}\nFor an equal-block BDLR operator\n\\[\nA=D+UV^*,\n\\]\nwith dimension $n$, block width $b$, and rank $r$, the stored scalar count is\n\\[\n\\boxed{n(b+2r)}\n\\]\nin place of $n^2$.","\\begin{proposition}[BDLR representation reduction]\nIf $b+2r<n$, BDLR storage reduces the scalar count by\n\\[\n\\boxed{\\frac{n}{b+2r}.}\n\\]\nThe same factor appears in the ideal apply count for a fixed number of right-hand sides.\n\\end{proposition}","\\begin{proof}\nThe block-diagonal part stores $(n/b)b^2=nb$ scalars. The two rank factors store $2nr$. The total is $n(b+2r)$. A full array stores $n^2$ scalars.\n\\end{proof}","\\begin{figure}[H]\n\\centering\n\\includegraphics[width=0.76\\linewidth]{16_representation_memory.pdf}\n\\caption{Stored BDLR representation for the model case $n=8192$, $b=64$, and $r=8$.}\n\\end{figure}","\\section{PSM mesh}\nEach compute chiplet uses a $4\\times4$ mesh of Packet Streaming Multiprocessors. Routers support unicast, multicast, and tree reduction. Multicast distributes low-rank factors, Kronecker factors, and transform data. Reduction combines destination contributions, small contractions, posterior scores, and residuals.","\\section{Local refinement}\nSuppose a parent packet task $v$ is replaced by an acyclic child module $H=(W,F)$. Predecessors of $v$ connect to child entries. Child exits connect to successors of $v$.","\\begin{theorem}[Topological splice]\nLet $\\prec$ be a topological order of the original graph and let $\\prec_H$ be a topological order of the child module. Replacing $v$ in $\\prec$ by $\\prec_H$ gives a topological order of the refined graph. Every unaffected pair of context tasks keeps its relative order.\n\\end{theorem}","\\begin{proof}\nEvery context edge is unchanged. Every child edge is respected by $\\prec_H$. Every predecessor of $v$ appeared before $v$ and therefore before the inserted child order. Every successor appeared after $v$ and therefore after the inserted child order. Removing the inserted children restores the original context order.\n\\end{proof}","\\section{Exact analysis and synthesis}\nLet $U$ be unitary and let $E_\\alpha$ be coordinate selectors. The pulled-back projectors are\n\\[\nP_\\alpha=U^*E_\\alpha U.\n\\]\nThe hardware analysis applies $U$ and selects the coordinates. Synthesis scatters the selected coordinates and applies $U^*$.","\\begin{theorem}[Transform-atlas hardware contract]\nIf the selector family is complete, the analysis and synthesis command graphs satisfy\n\\[\n\\boxed{\\Scal\\Acal=I.}\n\\]\nIf the selector family is incomplete, the certificate must report the omitted-coordinate residual.\n\\end{theorem}","\\begin{proof}\nFor a complete selector family, $\\sum_\\alpha E_\\alpha=I$. Hence\n\\[\n\\Scal\\Acal x\n=U^*\\left(\\sum_\\alpha E_\\alpha\\right)Ux\n=U^*Ux\n=x.\n\\]\nThe incomplete case replaces the identity by the declared selector sum.\n\\end{proof}","\\section{BDLR dataflow}\nFor\n\\[\nA=D+UV^*,\n\\]\nthe apply is\n\\[\nAX=DX+U(V^*X).\n\\]\nThe diagonal blocks remain distributed. The $r\\times q$ contraction is reduced and broadcast.","\\begin{theorem}[BDLR apply count]\nFor $q$ right-hand sides and equal packet width $b$, the modeled arithmetic count is\n\\[\n\\boxed{2qn(b+2r).}\n\\]\nA dense apply requires $2qn^2$ operations.\n\\end{theorem}","\\begin{proof}\nThe block-diagonal product costs $2qnb$. The contraction $V^*X$ costs $2nrq$. Multiplication by $U$ costs another $2nrq$. Adding the terms does not change the leading expression.\n\\end{proof}","\\section{Where BDLR remains useful}\nThe low-rank path is not uniformly favorable. Its benefit depends on block width, correction rank, right-hand-side count, and factor reuse. The reference model sweeps a range of block sizes and ranks while holding $n=8192$ and $q=32$ fixed.","\\section{Woodbury solve}\nThe chip uses packet solves with $D_\\alpha$ and one small dense correction:\n\\[\n(D+UV^*)^{-1}\n=D^{-1}-D^{-1}U(I+V^*D^{-1}U)^{-1}V^*D^{-1}.\n\\]\nThe solver engines handle the rank-sized middle system.","\\begin{theorem}[Packet error bound]\nLet\n\\[\nA=\\sum_{e\\in E}A_e,\n\\qquad\n\\widehat A=\\sum_{e\\in E}(A_e+E_e).\n\\]\nIf edge $e$ starts in packet $\\alpha(e)$, then\n\\[\n\\boxed{\n\\norm{(\\widehat A-A)x}\n\\le\n\\sum_{e\\in E}\\norm{E_e}\\norm{P_{\\alpha(e)}x}.}\n\\]\n\\end{theorem}","\\begin{proof}\nExact packet reconstruction gives\n\\[\n(\\widehat A-A)x=\\sum_eE_eP_{\\alpha(e)}x.\n\\]\nThe triangle inequality gives the bound.\n\\end{proof}","\\section{Precision allocation}\nUnder a logarithmic cost model and total error budget $\\tau$, the continuous allocation is\n\\[\n\\varepsilon_e\n=\\frac{\\tau c_e}{s_e\\sum_f c_f},\n\\]\nwhere $s_e$ is sensitivity and $c_e$ is cost. The compiler maps the result to supported formats.","\\section{Why this belongs on the chip}\nThe arithmetic calculus and the signal calculus share the same structural operations:\n\\[\n\\text{residue packet}\n\\to\n\\text{transfer}\n\\to\n\\text{refinement}\n\\to\n\\text{weighted reconstruction}.\n\\]\nThe exact arithmetic path is smaller than the floating-point path, but it allows the same descriptor and graph system to execute p-adic, recurrence, and finite-field packet workloads.","\\section{Worked BDLR compilation}\nA BDLR operator enters the compiler as the typed identity $A=D+UV^*$. No explicit matrix is constructed. The legality pass checks dimensions and the requested output form. The representation pass keeps the factors. Placement co-locates each diagonal block with the corresponding rows of $U$ and $V$. Precision is assigned per transfer contribution. The schedule computes $DX$, reduces $V^*X$, broadcasts the small contraction, and forms $U(V^*X)$ locally.","on{Worked BDLR compilation}\nA BDLR operator enters the compiler as the typed identity $A=D+UV^*$. No explicit matrix is constructed. The legality pass checks dimensions and the requested output form. The representation pass keeps the factors. Placement co-locates each diagonal block with the corresponding rows of $U$ and $V$. Precision is assigned per transfer contribution. The schedule computes $DX$, reduces $V^*X$, broadcasts the small contraction, and forms $U(V^*X)$ locally.","compilation}\nA BDLR operator enters the compiler as the typed identity $A=D+UV^*$. No explicit matrix is constructed. The legality pass checks dimensions and the requested output form. The representation pass keeps the factors. Placement co-locates each diagonal block with the corresponding rows of $U$ and $V$. Precision is assigned per transfer contribution. The schedule computes $DX$, reduces $V^*X$, broadcasts the small contraction, and forms $U(V^*X)$ locally.","the typed identity $A=D+UV^*$. No explicit matrix is constructed. The legality pass checks dimensions and the requested output form. The representation pass keeps the factors. Placement co-locates each diagonal block with the corresponding rows of $U$ and $V$. Precision is assigned per transfer contribution. The schedule computes $DX$, reduces $V^*X$, broadcasts the small contraction, and forms $U(V^*X)$ locally.","\\section{Block diagonal plus low rank}\nThe host submits packet descriptors for the diagonal blocks and factor rows. The graph contains one block batch, one reduction for $V^*X$, one factor broadcast, one local update, and one certificate. The dense matrix is absent from the graph and from memory.","\\begin{theorem}[Certified commit]\nSuppose a command result is provisional until a certificate $c(y)$ is evaluated. If the commit controller releases $y$ only when $c(y)$ satisfies the declared acceptance rule, then every visible result has passed that rule. A failed result cannot satisfy a downstream completion token.\n\\end{theorem}","\\section{Four different sources of gain}\nA fair result must say what changed. The total route may improve because the mathematics removed work, because the same representation ran better on another device, because a kernel was fused or graph-replayed, or because one-time setup was amortized. These are different quantities:\n\\[\nS_{\\mathrm{total}}\n=\nS_{\\mathrm{representation}}\nS_{\\mathrm{architecture}}\nS_{\\mathrm{kernel}}\nS_{\\mathrm{amortization}}.\n\\]\nThis is a bookkeeping identity only when every factor comes from matched rows with the same output contract and timing scope. Otherwise the factors are reported separately.","\\section{Measured CUDA foundation}\nThe prior packet-GPU study contains 154 matched CPU and GPU rows. The recorded GPU is an RTX 3070 Ti Laptop GPU. For $n=8192$, block width $64$, and 32 right-hand sides, the equal-block packet path took $0.046032$ ms and was $14.8919\\times$ faster than the matched device-resident dense GPU row. For BDLR with rank eight, the standard packet path took $0.097280$ ms and CUDA Graph replay took $0.079872$ ms. The graph row was $10.9355\\times$ faster than the matched dense GPU row. The graph improvement over the standard packet path was about $1.218\\times$.","tion}\nThe prior packet-GPU study contains 154 matched CPU and GPU rows. The recorded GPU is an RTX 3070 Ti Laptop GPU. For $n=8192$, block width $64$, and 32 right-hand sides, the equal-block packet path took $0.046032$ ms and was $14.8919\\times$ faster than the matched device-resident dense GPU row. For BDLR with rank eight, the standard packet path took $0.097280$ ms and CUDA Graph replay took $0.079872$ ms. The graph row was $10.9355\\times$ faster than the matched dense GPU row. The graph improvement over the standard packet path was about $1.218\\times$.","contains 154 matched CPU and GPU rows. The recorded GPU is an RTX 3070 Ti Laptop GPU. For $n=8192$, block width $64$, and 32 right-hand sides, the equal-block packet path took $0.046032$ ms and was $14.8919\\times$ faster than the matched device-resident dense GPU row. For BDLR with rank eight, the standard packet path took $0.097280$ ms and CUDA Graph replay took $0.079872$ ms. The graph row was $10.9355\\times$ faster than the matched dense GPU row. The graph improvement over the standard packet path was about $1.218\\times$.","and 32 right-hand sides, the equal-block packet path took $0.046032$ ms and was $14.8919\\times$ faster than the matched device-resident dense GPU row. For BDLR with rank eight, the standard packet path took $0.097280$ ms and CUDA Graph replay took $0.079872$ ms. The graph row was $10.9355\\times$ faster than the matched dense GPU row. The graph improvement over the standard packet path was about $1.218\\times$.","A compressed BDLR product at $n=1024$ took $0.1582$ ms. Materializing the explicit output took $0.5073$ ms. Those rows have different output contracts. The comparison shows the cost of requesting every entry. It is not a claim that one result is a faster implementation of the other.","\\section{Representation reduction}\nFor\n\\[\nA=D+UV^*,\n\\]\nwith dimension $n$, block width $b$, rank $r$, and $q$ right-hand sides, a factor-first application uses\n\\[\n2qn(b+2r)\n\\]\nmodeled operations and stores\n\\[\nn(b+2r)\n\\]\nscalars. The corresponding dense counts are $2qn^2$ and $n^2$. For\n\\[\nn=8192,\n\\qquad b=64,\n\\qquad r=8,\n\\qquad q=32,\n\\]\nthe arithmetic and storage reduction is\n\\[\n\\boxed{\\frac{n}{b+2r}=102.4.}\n\\]\nThis reduction belongs to the representation. A CUDA backend and a PRISM backend can both use it.","\\section{PRISM architecture model}\nThe architecture model uses\n\\[\nT=\n\\max\\left(\n\\frac{F}{\\eta_cP},\n\\frac{B}{\\eta_bW}\n\\right)\n+T_{\\mathrm{graph}},\n\\]\nwhere $F$ is arithmetic, $B$ is data movement, $P$ is peak arithmetic, $W$ is bandwidth, and $\\eta_c$, $\\eta_b$ are efficiency factors. The model is used to decide which hardware paths are worth building. It is not a silicon measurement.","\\section{Total route model and architecture-only models}\nThe earlier dense-route comparison predicts $70.79$ microseconds for a dense application and $1.87$ microseconds for the PRISM BDLR route. The ratio is about $37.8$. This is a total route model. It includes representation reduction and therefore is not labeled PRISM-over-CUDA architecture gain.","\\midrule\nFused multi-atlas analysis & $14.73$ $\\mu$s & $8.96$ $\\mu$s","Polyphase edge recovery & $4.00$ $\\mu$s & $1.35$ $\\mu$s","Bayesian model portfolio & $427.93$ $\\mu$s & $300.52$ $\\mu$s","\\bottomrule\n\\end{tabular}\n\\end{center}\nThe corresponding modeled gains are $1.64\\times$, $2.96\\times$, and $1.42\\times$. These are the present estimates of what residency, fusion, local solvers, and packet scheduling may add after a structured representation is already in use.","\\begin{certificate}[Current executable result]\nThe behavioral and architecture model passes\n\\[\n\\boxed{18/18\\text{ self-tests}}\n\\]\nand the independent pytest suite passes\n\\[\n\\boxed{18/18\\text{ tests}.}\n\\]\nThe largest semantic residual is the BDLR comparison residual\n\\[\n1.42\\times10^{-14},\n\\]\nwhich is consistent with floating-point roundoff.\n\\end{certificate}","\\chapter{Final architecture statement}\nThe final design follows one principle:\n\\[\n\\boxed{\n\\text{Do not materialize, move, or schedule structure that the calculus has already declared inactive.}\n}\n\\]\nThe machine executes\n\\[\n\\begin{aligned}\n\\text{seed object}\n&\\longrightarrow \\text{Packet IR}","\\chapter{Final architecture statement}\nThe final design follows one principle:\n\\[\n\\boxed{\n\\text{Do not materialize, move, or schedule structure that the calculus has already declared inactive.}\n}\n\\]\nThe machine executes\n\\[\n\\begin{aligned}\n\\text{seed object}\n&\\longrightarrow \\text{Packet IR}\\\\\n&\\longrightarrow \\text{mixed-representation plan}\\\\\n&\\longrightarrow \\text{packet warps on CUDA or PRISM}\\\\\n&\\longrightarrow \\text{local refinement and synthesis}\\\\\n&\\longrightarrow \\text{certificate and commit}.\n\\end{aligned}\n\\]\nPRISM-1 is a CUDA-like packet-programmable processor, not a dense-matrix preservation machine. Its hardware state may be a factor graph, transform chain, packet tree, sparse operator, explicit array, or mixture of those forms. The requested output contract determines what must be returned.","Execution group & $16\\times16$ matrix array plus programmable vector lanes"]}